URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] - Rev 24

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4611d 21h	/
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4697d 08h	/
22	Correct revision, compiles with VCS.	rehayes	4697d 08h	/
21	Simple language upgrade	rehayes	4698d 01h	/
20	minor update for timing constraint sugestions.	rehayes	5233d 02h	/
19	Minor change to add parameter to pit instance	rehayes	5233d 03h	/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5233d 06h	/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5247d 02h	/
16	Added master error counter variable, added simulation timout limit	rehayes	5358d 05h	/
15	Fix blocking assigment	rehayes	5386d 05h	/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5455d 03h	/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5485d 07h	/
12	Fixed for single cycle reads	rehayes	5486d 02h	/
11	Changed read task to capture data at rising edge of clock	rehayes	5486d 02h	/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5487d 05h	/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5492d 22h	/
8	Fix ack signal in testbench	rehayes	5492d 23h	/
7	Reflection of minor corrections	rehayes	5497d 05h	/
6	Reflection of minor corrections	rehayes	5497d 05h	/
5		rehayes	5535d 01h	/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5535d 01h	/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5535d 02h	/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5535d 02h	/
1	The project was created and the structure was created	root	5535d 17h	/

Browse

Tools

Subversion Repositories pit

[/] - Rev 24

Filtering Options