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Subversion Repositories sdr_ctrl

[/] - Rev 73

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Rev Log message Author Age Path
73 sdram bug in FPGA mode + 8/16 bit address map fix dinesha 1008d 20h /
72 Command Clean up for model-sim mode dinesha 4002d 05h /
71 Warning cleanup dinesha 4053d 21h /
70 Warning Cleanup dinesha 4053d 21h /
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4053d 22h /
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4053d 22h /
67 time scale removed dinesha 4123d 20h /
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4371d 21h /
65 Updated Log file with CAS latency support 4,5 dinesha 4372d 05h /
64 CAS Latency support added for 4,5 dinesha 4372d 05h /
63 FPGA Bench mark results are added dinesha 4491d 04h /
62 Synthesis constraint for simplify dinesha 4491d 04h /
61 RTL file list are added into SVN dinesha 4491d 05h /
60 warning cleanup dinesha 4491d 05h /
59 Control path request and data are register now for better FPGA timing dinesha 4491d 05h /
58 Read Data is register on RD_FAST=0 case dinesha 4491d 05h /
57 Synthesis constraints are added dinesha 4491d 20h /
56 FPGA Synth optimisation dinesha 4491d 21h /
55 FPGA Synthesis timing optimisation dinesha 4491d 21h /
54 FPGA Timing Optimisation dinesha 4494d 19h /
53 Test bench upgradation dinesha 4495d 19h /
52 Documentation update for request control and transfer control block dinesha 4495d 19h /
51 FPGA relating timing optimisation done dinesha 4495d 19h /
50 Bug fix the request length is fixe dinesha 4497d 23h /
49 clean up dinesha 4498d 22h /
48 top-level cleanup dinesha 4498d 22h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4498d 22h /
46 test bench upgrade + rtl cleanup dinesha 4500d 23h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4501d 03h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4503d 01h /

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