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Rev Log message Author Age Path
32 New directory structure. root 5571d 13h /
31 Include flattening process, simplify build system. arif_endro 5783d 13h /
30 Clean up. arif_endro 5827d 18h /
29 Done fixing Makefile for Alliance. arif_endro 5827d 18h /
28 chip IO place. arif_endro 5828d 14h /
27 chip IO interface. arif_endro 5828d 14h /
26 Removed. arif_endro 5828d 14h /
25 IO place. arif_endro 5828d 14h /
24 Update to use Alliance CAD System by ASIM/LIP6/UMPC arif_endro 5828d 16h /
23 Disable clear signal. arif_endro 5828d 16h /
22 Update last bit output assignment method. arif_endro 5828d 16h /
21 This commit was manufactured by cvs2svn to create tag 'version_1_1'. 7013d 17h /
20 New Version arif_endro 7013d 17h /
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7019d 16h /
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7019d 18h /
17 Initial Checkin arif_endro 7027d 15h /
16 Changes constan and minor fix arif_endro 7030d 18h /
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7033d 16h /
14 *** empty log message *** arif_endro 7038d 14h /
13 Update License arif_endro 7049d 15h /
12 Update License
Change reset signal handle		 arif_endro 7049d 16h /
11 Update License
Change reset signal handle		 arif_endro 7049d 16h /
10 Added script for generating cos ROM. arif_endro 7059d 19h /
9 Added documentation arif_endro 7076d 18h /
8 This commit was manufactured by cvs2svn to create tag 'okinawa_1'. 7090d 18h /
7 To view chipscope exported output using ModelSim waveform window arif_endro 7090d 18h /
6 Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO) arif_endro 7091d 20h /
5 Added interface in/out and testing paralelly (e.g. square and triangular) arif_endro 7091d 20h /
4 Fix elsif and if statement arif_endro 7094d 14h /
3 This commit was manufactured by cvs2svn to create tag 'VSFR_1'. 7097d 20h /

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