URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] - Rev 47

Rev	Log message	Author	Age	Path
47	New directory structure.	root	5568d 16h	/
46	Made some bugfixes	andreas	6856d 08h	/
45	Fixed loopback break generation	jesus	7857d 11h	/
44	Added some missing features and fixed baud rate generator	jesus	7858d 00h	/
43	* empty log message *	jesus	7866d 12h	/
42	Fixed bus req/ack cycle	jesus	7866d 12h	/
41	Removed UNISIM library	jesus	7866d 12h	/
40	Cleanup	jesus	7866d 12h	/
39	Added -n option and component declaration	jesus	7894d 09h	/
38	Added Leonardo .ucf generation	jesus	7894d 09h	/
37	Changed to single register file	jesus	7894d 12h	/
36	Added component declaration	jesus	7894d 12h	/
35	Release 0242	jesus	7901d 00h	/
34	Updated for ISE 5.1	jesus	7901d 05h	/
33	Fixed typo	jesus	7910d 21h	/
32	Fixed for ISE 5.1	jesus	7910d 21h	/
31	Fixed generic name error	jesus	7913d 23h	/
30	Changed to xilinx specific RAM	jesus	7919d 23h	/
29	Fixed (IX/IY+d) timing and added all GB op-codes	jesus	7919d 23h	/
28	Adapted for zxgate	jesus	7920d 23h	/
27	Xilinx SSRAM, initial release	jesus	7920d 23h	/
26	Fixed instruction timing for POP and DJNZ	jesus	7934d 15h	/
25	IX/IY timing and ADC/SBC fix	jesus	7936d 01h	/
24	no message	jesus	7941d 21h	/
23	Fixed T2Write	jesus	7941d 22h	/
22	Added 8080 top level	jesus	7941d 22h	/
21	no message	jesus	7946d 21h	/
20	Updated for new T80s generic	jesus	7946d 21h	/
19	Initial version	jesus	7946d 21h	/
18	Added T2Write generic	jesus	7947d 03h	/