| Rev |
Log message |
Author |
Age |
Path |
| 41 |
Well, finally got ports to work properly without latches. Had to reimplement a specific more complex form of RAM basically. The code is horrid, but testcases pass |
earlz |
4393d 23h |
/ |
| 40 |
Design doesn't pass synthesis right now. Not for sure why.
Fixed bug with encoding of second opcode byte in assembler
Added testcase for toggle program |
earlz |
4395d 23h |
/ |
| 39 |
A lot of work in the assembler. It now supports nearly every opcode implemented and is a lot cleaner
Added a bootrom. There isn't really a point in testbenching this.. I'm not for sure how I would, and it will change so much in these early days that it'll be pointless I think
Everything should be ready to go for a test on actual hardware now! |
earlz |
4396d 22h |
/ |
| 38 |
Made it synthesize without latches |
earlz |
4397d 01h |
/ |
| 37 |
Worked on the assembler more
Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some |
earlz |
4398d 23h |
/ |
| 36 |
Assembler actually has a real opcode now |
earlz |
4399d 01h |
/ |
| 35 |
Added a little assembler ruby script. Basically, I plan on levaraging the power of Ruby as a DSL to very easily create an assembler, rather than having to parse everything myself. |
earlz |
4399d 09h |
/ |
| 34 |
Implemented load and store instructions (`mov reg, [reg]` and `mov [reg], reg` respectively) |
earlz |
4399d 23h |
/ |
| 33 |
Added more test cases for push/pop. More are still needed though
Fixed SP increment/decrementing
Added new opcode `mov reg,reg` so debugging isn't such a pain |
earlz |
4400d 03h |
/ |
| 32 |
Finished up changes needed to make memory reading actually work.
Push and Pop now work |
earlz |
4400d 04h |
/ |
| 31 |
Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. |
earlz |
4401d 00h |
/ |
| 30 |
After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle |
earlz |
4401d 00h |
/ |
| 29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4404d 07h |
/ |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4405d 02h |
/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4405d 07h |
/ |
| 26 |
Added extra check to make sure fetcher works properly after memory write |
earlz |
4405d 09h |
/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4405d 13h |
/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4406d 06h |
/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4406d 07h |
/ |
| 22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4406d 22h |
/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4406d 23h |
/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4407d 22h |
/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4408d 00h |
/ |
| 18 |
Finished memory controller |
earlz |
4411d 10h |
/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4411d 23h |
/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4415d 02h |
/ |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4416d 23h |
/ |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4417d 07h |
/ |
| 13 |
Forgot about the new library I added |
earlz |
4417d 10h |
/ |
| 12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4417d 11h |
/ |
