OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 48

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8227d 13h /
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8232d 15h /
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8233d 13h /
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8234d 13h /
44 fixed more typo bugs gorban 8248d 13h /
43 lsr1r error fixed. mohor 8248d 20h /
42 ti_int_pnd error fixed. mohor 8248d 20h /
41 ti_int_d error fixed. mohor 8248d 20h /
40 Synthesis bugs fixed. Some other minor changes gorban 8250d 22h /
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8252d 20h /
38 small update to test interrupts gorban 8253d 17h /
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8253d 17h /
36 no message mohor 8259d 01h /
35 Fixes to break and timeout conditions gorban 8260d 20h /
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8262d 18h /
33 Small synopsis fixes gorban 8272d 01h /
32 Changes data_out to be synchronous again as it should have been. gorban 8272d 19h /
31 small fix gorban 8273d 14h /
30 Modified port names again gorban 8327d 19h /
29 Things connected to parity changed.
Clock devider changed.		 mohor 8328d 14h /
28 FIFO was not cleared after the data was read bug fixed. mohor 8329d 02h /
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 19h /
26 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 19h /
25 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 19h /
24 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 19h /
23 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 20h /
22 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 20h /
21 Changed top level with new port names + includes in all files. gorban 8329d 20h /
20 typo bug fixes gorban 8332d 15h /
19 updated docs and port names gorban 8332d 16h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.