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Rev	Log message	Author	Age	Path
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8149d 03h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8149d 03h	/
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8149d 03h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8149d 03h	/
74	tf_overrun signal was disabled since it was not used	gorban	8154d 04h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8161d 03h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8174d 11h	/
71	Removed confusing comment	gorban	8186d 00h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8191d 08h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8199d 23h	/
68	lsr[7] was not showing overrun errors.	mohor	8203d 06h	/
67	Missing declaration of rf_push_q fixed.	mohor	8210d 06h	/
66	rx push changed to be only one cycle wide.	mohor	8210d 06h	/
65	Warnings fixed (unused signals removed).	mohor	8211d 11h	/
64	Warnings cleared.	mohor	8211d 12h	/
63	Synplicity was having troubles with the comment.	mohor	8211d 12h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8212d 11h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8213d 05h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8213d 09h	/
59	MSR register fixed.	mohor	8216d 06h	/
58	After reset modem status register MSR should be reset.	mohor	8216d 10h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8217d 09h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8217d 10h	/
55	some synthesis bugs fixed	gorban	8217d 21h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8218d 11h	/
53	Scratch register define added.	mohor	8219d 11h	/
52	Scratch register added	gorban	8220d 00h	/
51	Igor fixed break condition bugs	gorban	8220d 00h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8224d 05h	/
49	committed the debug interface file	gorban	8225d 22h	/

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