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Rev Log message Author Age Path
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7372d 02h /
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7372d 02h /
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7372d 02h /
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7372d 02h /
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7485d 19h /
91 Removed files due to new complete testbench. tadejm 7486d 10h /
90 Add Flextronics header avisha 7488d 17h /
89 adjusted comment + define dries 7568d 22h /
88 added clearing the receiver fifo statuses on resets gorban 7631d 11h /
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7661d 13h /
86 restored include for uart_defines.v in uart_test.v gorban 7931d 17h /
85 Updated documentation to include latest changes. gorban 7965d 09h /
84 The uart_defines.v file is included again in sources. gorban 7978d 09h /
83 Reverted to include uart_defines.v file in other files again. gorban 7978d 09h /
82 Updated to work with latest core. gorban 7985d 06h /
81 Added lastest additions. gorban 7985d 07h /
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7985d 07h /
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7985d 07h /
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8138d 13h /
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8138d 13h /
76 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 8138d 13h /
75 Endian define added. Big Byte Endian is selected by default. mohor 8138d 13h /
74 tf_overrun signal was disabled since it was not used gorban 8143d 14h /
73 major bug in 32-bit mode that prevented register access fixed. gorban 8150d 13h /
72 UART PHY added. Files are fully operational, working on HW. mohor 8163d 21h /
71 Removed confusing comment gorban 8175d 10h /
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8180d 18h /
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8189d 09h /
68 lsr[7] was not showing overrun errors. mohor 8192d 16h /
67 Missing declaration of rf_push_q fixed. mohor 8199d 16h /

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