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Subversion Repositories xge_mac

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Rev Log message Author Age Path
31 Add more install info to README.TXT antanguay 2646d 00h /
30 Changes to testbench to support Icarus simulator antanguay 4154d 09h /
29 Adding parameter for max frame size antanguay 4160d 23h /
28 Adding parameter for max frame size antanguay 4160d 23h /
27 Fix octets stats on barrel shift transitions antanguay 4209d 23h /
26 Fix packet count antanguay 4215d 23h /
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4216d 01h /
24 Use FIFO's for statistics clock domain crossing antanguay 4216d 02h /
23 Adding basic packet stats antanguay 4216d 08h /
22 Added prototype system verilog testbench antanguay 4218d 05h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4218d 05h /
20 Updates for Xilinx synthesis antanguay 4507d 23h /
19 Updates for 32/64 bit systems antanguay 4683d 00h /
18 Updates for linux 32-bit antanguay 4683d 21h /
17 Fixed deprecated SystemC warnings antanguay 4686d 05h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4686d 11h /
15 Updated for Verilator 3.813 antanguay 4705d 12h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5294d 06h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5294d 07h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5294d 07h /
11 Fixed clock crossing antanguay 5400d 04h /
10 Added details to spec antanguay 5497d 23h /
9 Added old uploaded documents to new repository. root 5572d 11h /
8 Added old uploaded documents to new repository. root 5572d 16h /
7 New directory structure. root 5572d 16h /
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5849d 00h /
5 Fixed compilation antanguay 5855d 00h /
4 Created antanguay 5855d 03h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 5855d 04h /
2 Initial revision antanguay 5855d 04h /

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