URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 135

Rev	Log message	Author	Age	Path
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4617d 06h	/socgen/trunk/Makefile
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4653d 11h	/socgen/trunk/Makefile
96	hierConnections now create ports	jt_eaton	4727d 07h	/socgen/trunk/Makefile
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4763d 06h	/socgen/trunk/Makefile
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4789d 06h	/socgen/trunk/Makefile
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4886d 13h	/socgen/trunk/Makefile
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4901d 07h	/socgen/trunk/Makefile
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	4969d 12h	/socgen/trunk/Makefile
57	Now generate all filelists from xml files	jt_eaton	5002d 08h	/socgen/trunk/Makefile
56	soc_builder now builds verilog from xml files	jt_eaton	5007d 17h	/socgen/trunk/Makefile