URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma] - Rev 47

Rev	Log message	Author	Age	Path
27	Fixed: * BUG 2580: Missing packets in receive (PC => FPGA) path Changed: * Client tags now handled by Xilinx IP core * fifo signals to reflect upfifo and downfifo naming	fransschreuder	3094d 00h	/virtex7_pcie_dma
26	Added sys_clk constraint	fransschreuder	3094d 03h	/virtex7_pcie_dma
25	Added scripts and constraints for KCU105	fransschreuder	3094d 03h	/virtex7_pcie_dma
24	Added: * Support for KCU105 board in code TODO * Add constraints and build scripts for KCU105	fransschreuder	3094d 20h	/virtex7_pcie_dma
23	Fixed reset of application registers	fransschreuder	3152d 02h	/virtex7_pcie_dma
22	Added dma_soft_reset to trigger register resets	fransschreuder	3158d 02h	/virtex7_pcie_dma
21	Fixed BUG http://opencores.org/bug,view,2562	fransschreuder	3166d 23h	/virtex7_pcie_dma
20	Fixed: * Missing packets if the fifo goes empty during a TLP * Dynamically change the empty threshold of the main fifo to TLP size	fransschreuder	3180d 22h	/virtex7_pcie_dma
19	* driver/README updated	oussamak	3186d 23h	/virtex7_pcie_dma
18	Changed: * Added drivers * Added Wupper tools for debugging * Added card ID register	oussamak	3187d 01h	/virtex7_pcie_dma