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Subversion Repositories vg_z80_sbc

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Rev Log message Author Age Path
17 Clean up comments/whitespace. hharte 5660d 05h /
16 Boots Vector Graphic CP/M 2.2 from FLASH disk image.
Added ISE Project files, MCS and BIT files for programming the FPGA.		 hharte 5660d 10h /
15 Constraint file for S3E Starter Kit hharte 5660d 10h /
14 Deleted, moved to S3E SK Directory. hharte 5660d 10h /
13 Changed I/O addressing so addresses are not shifted left by two bits.
Commented out DDR controller, and replaced with 8K of SRAM.
Replaced FLASH memory interface with 4K SRAM.
Added Vector HD/FD Disk Controller, using FLASH memory for storage.

This design can now boot Vector Graphic 56K CP/M 2.2. But be aware
that there is only 12K in the TPA, since the Spartan3E does not have
enough block RAM to make more.

This system is enough to test the Z80 core more thorougly. The
EXZ80ALL.COM program on the included disk image tests all documented
Z80 instructions. Some tests pass, some don't. This means there is
more work to be done on the wb_z80 core.		 hharte 5660d 10h /
12 Initial implementation of a Vector Graphic HD/FD Disk Controller
with Wishbone interface. See the PDF in /doc for more information
about this controller.

For now, the storage is implemented in FLASH memory, which is read-only
to the controller. Also, the controller does not check (CRC) the disk
sector data, like the original does. Instead, it inserts 00's where the
CRC goes, to simulate a correctly checked CRC.

I am able to boot CP/M 2.2 using this controller, with the vgboot.mcs image
programmed into FLASH. See the diskimage/ directory.		 hharte 5660d 10h /
11 Fully parameterize so different size SRAMs can be instantiated. hharte 5660d 10h /
10 Change address mapping for I/O cycles. hharte 5660d 10h /
9 Change default mapping.
Update address decoding for I/O Space.		 hharte 5660d 10h /
8 CLarified the instructions a bit, and added some Internet links. hharte 5660d 15h /

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