URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] - Rev 41

Rev	Log message	Author	Age	Path
21	Since all BRAM is unified in one component, this testbench is not necessary anymore.	lcdsgmtr	3159d 13h	/
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3159d 13h	/
19	Makefile for building memory block testbench.	lcdsgmtr	3159d 13h	/
18	Ignore work files from GHDL.	lcdsgmtr	3159d 13h	/
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3159d 13h	/
16	Re-write of memory in function of initial array memory blocks.	lcdsgmtr	3159d 13h	/
15	Unification of all RAM parts into one interface.	lcdsgmtr	3159d 13h	/
14	Simple implementation project.	lcdsgmtr	3291d 12h	/
13	Updated smallest Xilinx configuration.	lcdsgmtr	3291d 12h	/
12	Update Xilinx configurations.	lcdsgmtr	3291d 12h	/