URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] - Rev 86

Rev	Log message	Author	Age	Path
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4557d 13h	/amber/trunk/hw/
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4627d 11h	/amber/trunk/hw/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4627d 14h	/amber/trunk/hw/
57	Add some debug messages	csantifort	4627d 14h	/amber/trunk/hw/
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4627d 14h	/amber/trunk/hw/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4644d 14h	/amber/trunk/hw/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4659d 12h	/amber/trunk/hw/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4659d 12h	/amber/trunk/hw/
50	Revert to previous version	csantifort	4700d 12h	/amber/trunk/hw/
49	Added a note n how to change timeouts	csantifort	4700d 12h	/amber/trunk/hw/