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[/] [rio/] - Rev 40

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Rev Log message Author Age Path
20 Adding software C-stack and matching VHDL modules. magro732 3922d 08h /rio/
19 Removing synthesis warnings. magro732 3947d 07h /rio/
18 Making RioSerial entity the same as before+minor fixes. magro732 3948d 06h /rio/
17 Removing latch and improving timing. magro732 3949d 06h /rio/
16 Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing. magro732 3949d 07h /rio/
15 All testcases are ok. Still needs some tweeks though. magro732 3953d 08h /rio/
14 Most issues solved, testbench issues remains. magro732 3956d 07h /rio/
13 Timeouts are working. magro732 3959d 08h /rio/
12 Backup of recent work, debugging new RioSerial. magro732 3970d 06h /rio/
11 Receiver ready, transmitter is compiling. magro732 3970d 07h /rio/

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