URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 73

Rev	Log message	Author	Age	Path
53	Test bench upgradation	dinesha	4500d 21h	/sdr_ctrl/
52	Documentation update for request control and transfer control block	dinesha	4500d 21h	/sdr_ctrl/
51	FPGA relating timing optimisation done	dinesha	4500d 22h	/sdr_ctrl/
50	Bug fix the request length is fixe	dinesha	4503d 02h	/sdr_ctrl/
49	clean up	dinesha	4504d 01h	/sdr_ctrl/
48	top-level cleanup	dinesha	4504d 01h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4504d 01h	/sdr_ctrl/
46	test bench upgrade + rtl cleanup	dinesha	4506d 01h	/sdr_ctrl/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4506d 06h	/sdr_ctrl/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4508d 04h	/sdr_ctrl/