URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [rtl/] - Rev 106

Rev	Log message	Author	Age	Path
66	rx push changed to be only one cycle wide.	mohor	8209d 07h	/uart16550/tags/rel_3/rtl/
65	Warnings fixed (unused signals removed).	mohor	8210d 11h	/uart16550/tags/rel_3/rtl/
64	Warnings cleared.	mohor	8210d 12h	/uart16550/tags/rel_3/rtl/
63	Synplicity was having troubles with the comment.	mohor	8210d 12h	/uart16550/tags/rel_3/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8211d 11h	/uart16550/tags/rel_3/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8212d 05h	/uart16550/tags/rel_3/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8212d 10h	/uart16550/tags/rel_3/rtl/
59	MSR register fixed.	mohor	8215d 07h	/uart16550/tags/rel_3/rtl/
58	After reset modem status register MSR should be reset.	mohor	8215d 10h	/uart16550/tags/rel_3/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8216d 10h	/uart16550/tags/rel_3/rtl/