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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 34

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Rev	Log message	Author	Age	Path
14	RENAMED: -- simulation folder	aborga	3245d 19h	/virtex7_pcie_dma/
13	RENAMED: -- script	aborga	3245d 19h	/virtex7_pcie_dma/
12	Fixed http://opencores.org/bug,view,2524	fransschreuder	3320d 18h	/virtex7_pcie_dma/
11	MODIFIED: -- updated documentation	aborga	3333d 16h	/virtex7_pcie_dma/
10	Changed: LOC => Package_pin	fransschreuder	3343d 17h	/virtex7_pcie_dma/
9	Added actual version information (Build date and svn revision) in BOARD_ID register	fransschreuder	3372d 15h	/virtex7_pcie_dma/
8	Changed: * Added support for circular DMA (wrap around) * Fixed Read / Write interrupts	fransschreuder	3372d 21h	/virtex7_pcie_dma/
7	Changed: * Simplified address calculation to relax timing * Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing * Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk * Added support for the High tech Global HTG710 board	fransschreuder	3412d 17h	/virtex7_pcie_dma/
6	Changed: * fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable * Fixed missing signals in sensitivity list	fransschreuder	3418d 15h	/virtex7_pcie_dma/
5	Changed: * Added two registers to test interrupts vectors 2 and 3 * Added a register to read generic constants to show number of interrupts / number of descriptors * fixed consistency of generic default values among different design units * fixed route of pll_locked / register map record, to allow non-flattening of synthesis	fransschreuder	3419d 19h	/virtex7_pcie_dma/

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