URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] [trunk/] - Rev 36

Rev	Log message	Author	Age	Path
16	MODIFED: -- top level name to wupper_oc (including scripts)	aborga	3250d 14h	/virtex7_pcie_dma/trunk/
15	MODIFIED: -- Renamed core to Wupper (vhdl files) -- Changed width of interrupt enable to number_of_interrupts	fransschreuder	3250d 14h	/virtex7_pcie_dma/trunk/
14	RENAMED: -- simulation folder	aborga	3250d 15h	/virtex7_pcie_dma/trunk/
13	RENAMED: -- script	aborga	3250d 15h	/virtex7_pcie_dma/trunk/
12	Fixed http://opencores.org/bug,view,2524	fransschreuder	3325d 15h	/virtex7_pcie_dma/trunk/
11	MODIFIED: -- updated documentation	aborga	3338d 13h	/virtex7_pcie_dma/trunk/
10	Changed: LOC => Package_pin	fransschreuder	3348d 14h	/virtex7_pcie_dma/trunk/
9	Added actual version information (Build date and svn revision) in BOARD_ID register	fransschreuder	3377d 12h	/virtex7_pcie_dma/trunk/
8	Changed: * Added support for circular DMA (wrap around) * Fixed Read / Write interrupts	fransschreuder	3377d 18h	/virtex7_pcie_dma/trunk/
7	Changed: * Simplified address calculation to relax timing * Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing * Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk * Added support for the High tech Global HTG710 board	fransschreuder	3417d 14h	/virtex7_pcie_dma/trunk/