URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 508

Rev	Log message	Author	Age	Path
488	ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added.	julius	4868d 05h	/
487	ORPSoC main software makefile update	julius	4871d 03h	/
486	ORPSoC updates, mainly software, i2c driver	julius	4871d 03h	/
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4875d 08h	/
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4876d 06h	/
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4878d 08h	/
482	Don't hardcode tool versions in help text	olof	4879d 20h	/
481	OR1200 Update. RTL and spec.	julius	4891d 15h	/
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4892d 12h	/
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4893d 12h	/