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21 Fix overrun and underrun interrupts bug

The overrun and underrun did not have any logic for
resetting their signals, this patch changes that so
that the interrupt signal is only on when the event
happens. The interrupt will be latched into
the interrupt status register anyway, so keeping it
high for (in worst case) one clock cycle is enough.
stekern 4702d 12h /
20 root 5500d 00h /
19 root 5556d 01h /
18 Added old uploaded documents to new repository. root 5556d 04h /
17 New directory structure. root 5556d 04h /
16 Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly. rudi 7863d 22h /
15 Updated copyright header. rudi 7920d 08h /
14 Fixed a bug reported by Igor. Apparently this bug only shows up when
the WB clock is very low (2x bit_clk). Updated Copyright header.
rudi 7920d 08h /
13 Changed the datasheet and STATUS.txt rudi 7920d 08h /
12 - Added defines to select fifo depth between 4, 8 and 16 entries. rudi 8112d 12h /
11 - fixed spelling rudi 8118d 10h /
10 - Fixed the order of the thrash hold bits to match the spec.
- Many minor synthesis cleanup items ...
rudi 8118d 10h /
9 *** empty log message *** rudi 8138d 06h /
8 Simulation Makefile rudi 8138d 06h /
7 Added test bench for public release rudi 8138d 07h /
6 - Removed RTY_O output.
- Added Clock and Reset Inputs to documentation.
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
rudi 8325d 07h /
5 Added Directory Tree Description to README file rudi 8328d 06h /
4 - Changed to new directory structure rudi 8332d 08h /
3 This commit was manufactured by cvs2svn to create tag 'start'. 8408d 12h /
2 Initial Checkin rudi 8408d 12h /

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