URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] - Rev 25

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Rev	Log message	Author	Age	Path
25	Added AXI Passthrough Monitor IP for Vivado IP Integrator. Can be synthesized by Vivado, but cannot be detected in the Vivado GUI. Tk GUI can run with ISE/PLanahead 14.3 or 14.7.	ash_riple	3540d 19h	/
24	Added support for Qsys based avalon transaction monitoring.	ash_riple	3560d 19h	/
23	Updated Altera Tcl script to 32bit address bus.	ash_riple	3767d 17h	/
22		ash_riple	3767d 23h	/
21		ash_riple	3768d 00h	/
20	Added support for 32bit Address bus.	ash_riple	3768d 00h	/
19	Minor changes.	ash_riple	4181d 19h	/
18	Added support for Xilinx Chips. Added support for AXI4-Lite bus. Can be used as an XPS IP.	ash_riple	4181d 19h	/
17	Added unreachable trigger condition "@WR & @RD" checking.	ash_riple	4427d 22h	/
16	Released version 2.2.	ash_riple	4449d 22h	/
15	Released version 2.2.	ash_riple	4449d 22h	/
14	Changed dec to hex value of triggerPnum.	ash_riple	4450d 13h	/
13	Added minor syntax changes and Linux environment simulation script.	ash_riple	4450d 19h	/
12	Added timing information to the capture content.	ash_riple	4451d 02h	/
11	Added pre-trigger capture.	ash_riple	4451d 18h	/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4456d 23h	/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4457d 18h	/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4461d 18h	/
7	Added references related to "Bus Monitor".	ash_riple	4461d 22h	/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4462d 18h	/

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[/] - Rev 25

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