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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [MC6809_cpu.v] - Rev 17

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Rev Log message Author Age Path
17 Bugfixes ale500 3503d 00h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
16 Fix ABX, TST, implemented new decoder, removed unused logic ale500 3590d 23h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
14 Improved speed and reduced decoder complexity ale500 3601d 04h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
12 Fixed inc, dec, indirect indexed, mul, shifts, h flag ale500 3615d 04h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
11 Fixed inc, dec, clr direct, ext and ind, deca, decb ale500 3618d 23h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
10 Fixed several extended and indirect opcodes ale500 3622d 04h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
9 Implemented E flag, some minor optimizations ale500 3796d 04h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
7 Added SYNC, Fixed EXG ale500 3797d 03h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
6 Implemented CWAI. Minor optimizations ale500 3801d 00h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
5 EXG/TFR Implemented ale500 3801d 21h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
4 Bugfix and enhancements ale500 3803d 02h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
2 Initial version ale500 3805d 00h /6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v

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