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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [decoders.v] - Rev 14

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Rev Log message Author Age Path
14 Improved speed and reduced decoder complexity ale500 3606d 08h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
12 Fixed inc, dec, indirect indexed, mul, shifts, h flag ale500 3620d 08h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
11 Fixed inc, dec, clr direct, ext and ind, deca, decb ale500 3624d 03h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
10 Fixed several extended and indirect opcodes ale500 3627d 08h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
9 Implemented E flag, some minor optimizations ale500 3801d 08h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
6 Implemented CWAI. Minor optimizations ale500 3806d 04h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
5 EXG/TFR Implemented ale500 3807d 00h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
4 Bugfix and enhancements ale500 3808d 06h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v
2 Initial version ale500 3810d 04h /6809_6309_compatible_core/trunk/rtl/verilog/decoders.v

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