URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Rev 123

Rev	Log message	Author	Age	Path
123	fiz bug iv pcs operation.	simont	7726d 00h	/8051/trunk/rtl/verilog/oc8051_alu.v
82	replace some modules	simont	7817d 00h	/8051/trunk/rtl/verilog/oc8051_alu.v
46	prepared header	simont	7921d 21h	/8051/trunk/rtl/verilog/oc8051_alu.v
22	fix some bugs	simont	7961d 19h	/8051/trunk/rtl/verilog/oc8051_alu.v
11	des2_r removed	simont	7966d 23h	/8051/trunk/rtl/verilog/oc8051_alu.v
10	% replaced with ^ in uart; some minor improvements	markom	7967d 05h	/8051/trunk/rtl/verilog/oc8051_alu.v
8	some IDS optimizations	markom	7968d 22h	/8051/trunk/rtl/verilog/oc8051_alu.v
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	7968d 23h	/8051/trunk/rtl/verilog/oc8051_alu.v
5	more linter corrections; 2 tests still fail	markom	7969d 01h	/8051/trunk/rtl/verilog/oc8051_alu.v
4	Code repaired to satisfy the linter; testbech fails	markom	7969d 03h	/8051/trunk/rtl/verilog/oc8051_alu.v
2	Initial CVS import	simont	7985d 01h	/8051/trunk/rtl/verilog/oc8051_alu.v