URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_b_register.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5506d 08h	/8051/trunk/rtl/verilog/oc8051_b_register.v
185		root	5562d 09h	/8051/trunk/rtl/verilog/oc8051_b_register.v
118	change wr_sft to 2 bit wire.	simont	7724d 06h	/8051/trunk/rtl/verilog/oc8051_b_register.v
116	change sfr's interface.	simont	7726d 08h	/8051/trunk/rtl/verilog/oc8051_b_register.v
82	replace some modules	simont	7810d 09h	/8051/trunk/rtl/verilog/oc8051_b_register.v
46	prepared header	simont	7915d 05h	/8051/trunk/rtl/verilog/oc8051_b_register.v
27	fix some bugs	simont	7953d 12h	/8051/trunk/rtl/verilog/oc8051_b_register.v
22	fix some bugs	simont	7955d 04h	/8051/trunk/rtl/verilog/oc8051_b_register.v
5	more linter corrections; 2 tests still fail	markom	7962d 10h	/8051/trunk/rtl/verilog/oc8051_b_register.v
4	Code repaired to satisfy the linter; testbech fails	markom	7962d 12h	/8051/trunk/rtl/verilog/oc8051_b_register.v
2	Initial CVS import	simont	7978d 09h	/8051/trunk/rtl/verilog/oc8051_b_register.v