URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_comp.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5513d 07h	/8051/trunk/rtl/verilog/oc8051_comp.v
185		root	5569d 09h	/8051/trunk/rtl/verilog/oc8051_comp.v
179	add /* synopsys xx_case */ to case statments.	simont	7648d 02h	/8051/trunk/rtl/verilog/oc8051_comp.v
132	change branch instruction execution (reduse needed clock periods).	simont	7715d 05h	/8051/trunk/rtl/verilog/oc8051_comp.v
95	updating...	simont	7738d 11h	/8051/trunk/rtl/verilog/oc8051_comp.v
46	prepared header	simont	7922d 05h	/8051/trunk/rtl/verilog/oc8051_comp.v
16	inputs ram and op2 removed	simont	7966d 09h	/8051/trunk/rtl/verilog/oc8051_comp.v
10	% replaced with ^ in uart; some minor improvements	markom	7967d 13h	/8051/trunk/rtl/verilog/oc8051_comp.v
9	removed unused compare states	markom	7969d 06h	/8051/trunk/rtl/verilog/oc8051_comp.v
2	Initial CVS import	simont	7985d 09h	/8051/trunk/rtl/verilog/oc8051_comp.v