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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 141

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141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7704d 09h /8051/trunk/rtl/verilog/oc8051_decoder.v
139 add aditional alu destination to solve critical path. simont 7705d 03h /8051/trunk/rtl/verilog/oc8051_decoder.v
132 change branch instruction execution (reduse needed clock periods). simont 7715d 02h /8051/trunk/rtl/verilog/oc8051_decoder.v
118 change wr_sft to 2 bit wire. simont 7731d 03h /8051/trunk/rtl/verilog/oc8051_decoder.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7731d 03h /8051/trunk/rtl/verilog/oc8051_decoder.v
82 replace some modules simont 7817d 05h /8051/trunk/rtl/verilog/oc8051_decoder.v
62 fix bugs in instruction interface simont 7899d 02h /8051/trunk/rtl/verilog/oc8051_decoder.v
54 cahnge interface to instruction rom simont 7905d 00h /8051/trunk/rtl/verilog/oc8051_decoder.v
46 prepared header simont 7922d 01h /8051/trunk/rtl/verilog/oc8051_decoder.v
40 added sigals for interacting with external ram simont 7942d 05h /8051/trunk/rtl/verilog/oc8051_decoder.v
23 mul & div use 4 clocks simont 7962d 00h /8051/trunk/rtl/verilog/oc8051_decoder.v
20 multiplier and divider changed so they complete in 4 cycles markom 7962d 07h /8051/trunk/rtl/verilog/oc8051_decoder.v
17 fix some bugs simont 7966d 05h /8051/trunk/rtl/verilog/oc8051_decoder.v
10 % replaced with ^ in uart; some minor improvements markom 7967d 10h /8051/trunk/rtl/verilog/oc8051_decoder.v
9 removed unused compare states markom 7969d 02h /8051/trunk/rtl/verilog/oc8051_decoder.v
8 some IDS optimizations markom 7969d 03h /8051/trunk/rtl/verilog/oc8051_decoder.v
5 more linter corrections; 2 tests still fail markom 7969d 06h /8051/trunk/rtl/verilog/oc8051_decoder.v
4 Code repaired to satisfy the linter; testbech fails markom 7969d 08h /8051/trunk/rtl/verilog/oc8051_decoder.v
2 Initial CVS import simont 7985d 06h /8051/trunk/rtl/verilog/oc8051_decoder.v

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