URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 23

Rev	Log message	Author	Age	Path
23	mul & div use 4 clocks	simont	7962d 09h	/8051/trunk/rtl/verilog/oc8051_decoder.v
20	multiplier and divider changed so they complete in 4 cycles	markom	7962d 17h	/8051/trunk/rtl/verilog/oc8051_decoder.v
17	fix some bugs	simont	7966d 15h	/8051/trunk/rtl/verilog/oc8051_decoder.v
10	% replaced with ^ in uart; some minor improvements	markom	7967d 19h	/8051/trunk/rtl/verilog/oc8051_decoder.v
9	removed unused compare states	markom	7969d 12h	/8051/trunk/rtl/verilog/oc8051_decoder.v
8	some IDS optimizations	markom	7969d 12h	/8051/trunk/rtl/verilog/oc8051_decoder.v
5	more linter corrections; 2 tests still fail	markom	7969d 16h	/8051/trunk/rtl/verilog/oc8051_decoder.v
4	Code repaired to satisfy the linter; testbech fails	markom	7969d 17h	/8051/trunk/rtl/verilog/oc8051_decoder.v
2	Initial CVS import	simont	7985d 15h	/8051/trunk/rtl/verilog/oc8051_decoder.v