URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 82

Rev	Log message	Author	Age	Path
82	replace some modules	simont	7812d 03h	/8051/trunk/rtl/verilog/oc8051_decoder.v
62	fix bugs in instruction interface	simont	7894d 00h	/8051/trunk/rtl/verilog/oc8051_decoder.v
54	cahnge interface to instruction rom	simont	7899d 22h	/8051/trunk/rtl/verilog/oc8051_decoder.v
46	prepared header	simont	7917d 00h	/8051/trunk/rtl/verilog/oc8051_decoder.v
40	added sigals for interacting with external ram	simont	7937d 04h	/8051/trunk/rtl/verilog/oc8051_decoder.v
23	mul & div use 4 clocks	simont	7956d 22h	/8051/trunk/rtl/verilog/oc8051_decoder.v
20	multiplier and divider changed so they complete in 4 cycles	markom	7957d 06h	/8051/trunk/rtl/verilog/oc8051_decoder.v
17	fix some bugs	simont	7961d 04h	/8051/trunk/rtl/verilog/oc8051_decoder.v
10	% replaced with ^ in uart; some minor improvements	markom	7962d 08h	/8051/trunk/rtl/verilog/oc8051_decoder.v
9	removed unused compare states	markom	7964d 01h	/8051/trunk/rtl/verilog/oc8051_decoder.v
8	some IDS optimizations	markom	7964d 01h	/8051/trunk/rtl/verilog/oc8051_decoder.v
5	more linter corrections; 2 tests still fail	markom	7964d 04h	/8051/trunk/rtl/verilog/oc8051_decoder.v
4	Code repaired to satisfy the linter; testbech fails	markom	7964d 06h	/8051/trunk/rtl/verilog/oc8051_decoder.v
2	Initial CVS import	simont	7980d 04h	/8051/trunk/rtl/verilog/oc8051_decoder.v