URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Rev 118

Rev	Log message	Author	Age	Path
118	change wr_sft to 2 bit wire.	simont	7731d 08h	/8051/trunk/rtl/verilog/oc8051_defines.v
114	remove t2mod register	simont	7736d 14h	/8051/trunk/rtl/verilog/oc8051_defines.v
93	OC8051_XILINX_RAM added	simont	7738d 13h	/8051/trunk/rtl/verilog/oc8051_defines.v
82	replace some modules	simont	7817d 10h	/8051/trunk/rtl/verilog/oc8051_defines.v
67	add parameters for instruction cache	simont	7898d 11h	/8051/trunk/rtl/verilog/oc8051_defines.v
9	removed unused compare states	markom	7969d 08h	/8051/trunk/rtl/verilog/oc8051_defines.v
2	Initial CVS import	simont	7985d 11h	/8051/trunk/rtl/verilog/oc8051_defines.v