URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Rev 141

Rev	Log message	Author	Age	Path
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7697d 11h	/8051/trunk/rtl/verilog/oc8051_defines.v
139	add aditional alu destination to solve critical path.	simont	7698d 05h	/8051/trunk/rtl/verilog/oc8051_defines.v
132	change branch instruction execution (reduse needed clock periods).	simont	7708d 03h	/8051/trunk/rtl/verilog/oc8051_defines.v
126	define OC8051_XILINX_RAMB added	simont	7717d 11h	/8051/trunk/rtl/verilog/oc8051_defines.v
122	deifne OC8051_ROM added	simont	7722d 11h	/8051/trunk/rtl/verilog/oc8051_defines.v
120	defines for pherypherals added	simont	7723d 08h	/8051/trunk/rtl/verilog/oc8051_defines.v
118	change wr_sft to 2 bit wire.	simont	7724d 04h	/8051/trunk/rtl/verilog/oc8051_defines.v
114	remove t2mod register	simont	7729d 10h	/8051/trunk/rtl/verilog/oc8051_defines.v
93	OC8051_XILINX_RAM added	simont	7731d 09h	/8051/trunk/rtl/verilog/oc8051_defines.v
82	replace some modules	simont	7810d 06h	/8051/trunk/rtl/verilog/oc8051_defines.v
67	add parameters for instruction cache	simont	7891d 07h	/8051/trunk/rtl/verilog/oc8051_defines.v
9	removed unused compare states	markom	7962d 04h	/8051/trunk/rtl/verilog/oc8051_defines.v
2	Initial CVS import	simont	7978d 07h	/8051/trunk/rtl/verilog/oc8051_defines.v