URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Rev 172

Rev	Log message	Author	Age	Path
172	BIST signals added.	simont	7662d 12h	/8051/trunk/rtl/verilog/oc8051_defines.v
149	pipelined acces to axternal instruction interface added.	simont	7676d 09h	/8051/trunk/rtl/verilog/oc8051_defines.v
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7704d 16h	/8051/trunk/rtl/verilog/oc8051_defines.v
139	add aditional alu destination to solve critical path.	simont	7705d 10h	/8051/trunk/rtl/verilog/oc8051_defines.v
132	change branch instruction execution (reduse needed clock periods).	simont	7715d 09h	/8051/trunk/rtl/verilog/oc8051_defines.v
126	define OC8051_XILINX_RAMB added	simont	7724d 16h	/8051/trunk/rtl/verilog/oc8051_defines.v
122	deifne OC8051_ROM added	simont	7729d 16h	/8051/trunk/rtl/verilog/oc8051_defines.v
120	defines for pherypherals added	simont	7730d 13h	/8051/trunk/rtl/verilog/oc8051_defines.v
118	change wr_sft to 2 bit wire.	simont	7731d 10h	/8051/trunk/rtl/verilog/oc8051_defines.v
114	remove t2mod register	simont	7736d 15h	/8051/trunk/rtl/verilog/oc8051_defines.v
93	OC8051_XILINX_RAM added	simont	7738d 15h	/8051/trunk/rtl/verilog/oc8051_defines.v
82	replace some modules	simont	7817d 12h	/8051/trunk/rtl/verilog/oc8051_defines.v
67	add parameters for instruction cache	simont	7898d 13h	/8051/trunk/rtl/verilog/oc8051_defines.v
9	removed unused compare states	markom	7969d 09h	/8051/trunk/rtl/verilog/oc8051_defines.v
2	Initial CVS import	simont	7985d 13h	/8051/trunk/rtl/verilog/oc8051_defines.v