URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Rev 118

Rev	Log message	Author	Age	Path
118	change wr_sft to 2 bit wire.	simont	7724d 06h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
81	initial import	simont	7810d 08h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v