URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Rev 173

Rev	Log message	Author	Age	Path
173	simualtion `ifdef added	simont	7652d 08h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
158	fix bug.	simont	7667d 10h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
149	pipelined acces to axternal instruction interface added.	simont	7669d 04h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
146	fix bug in movc intruction.	simont	7691d 05h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
140	cahnge assigment to pc_wait (remove istb_o)	simont	7697d 12h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
139	add aditional alu destination to solve critical path.	simont	7698d 05h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
132	change branch instruction execution (reduse needed clock periods).	simont	7708d 04h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
128	chance idat_ir to 24 bit wide	simont	7717d 11h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
121	Change pc add value from 23'h to 16'h	simont	7722d 11h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
118	change wr_sft to 2 bit wire.	simont	7724d 05h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v
81	initial import	simont	7810d 07h	/8051/trunk/rtl/verilog/oc8051_memory_interface.v