URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5513d 08h	/8051/trunk/rtl/verilog/oc8051_psw.v
185		root	5569d 09h	/8051/trunk/rtl/verilog/oc8051_psw.v
179	add /* synopsys xx_case */ to case statments.	simont	7648d 02h	/8051/trunk/rtl/verilog/oc8051_psw.v
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7731d 07h	/8051/trunk/rtl/verilog/oc8051_psw.v
116	change sfr's interface.	simont	7733d 08h	/8051/trunk/rtl/verilog/oc8051_psw.v
82	replace some modules	simont	7817d 09h	/8051/trunk/rtl/verilog/oc8051_psw.v
76	add module oc8051_sfr, 256 bytes internal ram	simont	7886d 06h	/8051/trunk/rtl/verilog/oc8051_psw.v
46	prepared header	simont	7922d 05h	/8051/trunk/rtl/verilog/oc8051_psw.v
27	fix some bugs	simont	7960d 12h	/8051/trunk/rtl/verilog/oc8051_psw.v
22	fix some bugs	simont	7962d 04h	/8051/trunk/rtl/verilog/oc8051_psw.v
6	psw combinatorial loop removed	markom	7969d 10h	/8051/trunk/rtl/verilog/oc8051_psw.v
5	more linter corrections; 2 tests still fail	markom	7969d 10h	/8051/trunk/rtl/verilog/oc8051_psw.v
4	Code repaired to satisfy the linter; testbech fails	markom	7969d 12h	/8051/trunk/rtl/verilog/oc8051_psw.v
2	Initial CVS import	simont	7985d 09h	/8051/trunk/rtl/verilog/oc8051_psw.v