URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5514d 00h	/8051/trunk/rtl/verilog/oc8051_sfr.v
185		root	5570d 01h	/8051/trunk/rtl/verilog/oc8051_sfr.v
179	add /* synopsys xx_case */ to case statments.	simont	7648d 19h	/8051/trunk/rtl/verilog/oc8051_sfr.v
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7704d 03h	/8051/trunk/rtl/verilog/oc8051_sfr.v
139	add aditional alu destination to solve critical path.	simont	7706d 00h	/8051/trunk/rtl/verilog/oc8051_sfr.v
134	fix bug in case execution of two data dependent instructions.	simont	7712d 04h	/8051/trunk/rtl/verilog/oc8051_sfr.v
132	change branch instruction execution (reduse needed clock periods).	simont	7715d 22h	/8051/trunk/rtl/verilog/oc8051_sfr.v
120	defines for pherypherals added	simont	7731d 03h	/8051/trunk/rtl/verilog/oc8051_sfr.v
118	change wr_sft to 2 bit wire.	simont	7731d 23h	/8051/trunk/rtl/verilog/oc8051_sfr.v
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7732d 00h	/8051/trunk/rtl/verilog/oc8051_sfr.v
116	change sfr's interface.	simont	7734d 00h	/8051/trunk/rtl/verilog/oc8051_sfr.v
115	change uart to meet timing.	simont	7734d 02h	/8051/trunk/rtl/verilog/oc8051_sfr.v
113	signal prsc_ow added.	simont	7737d 05h	/8051/trunk/rtl/verilog/oc8051_sfr.v
90	change module name.	simont	7743d 22h	/8051/trunk/rtl/verilog/oc8051_sfr.v
87	add include oc8051_defines.v	simont	7810d 01h	/8051/trunk/rtl/verilog/oc8051_sfr.v
82	replace some modules	simont	7818d 01h	/8051/trunk/rtl/verilog/oc8051_sfr.v
75	initial import	simont	7886d 22h	/8051/trunk/rtl/verilog/oc8051_sfr.v