URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5513d 07h	/8051/trunk/rtl/verilog/oc8051_tc.v
185		root	5569d 08h	/8051/trunk/rtl/verilog/oc8051_tc.v
179	add /* synopsys xx_case */ to case statments.	simont	7648d 02h	/8051/trunk/rtl/verilog/oc8051_tc.v
120	defines for pherypherals added	simont	7730d 10h	/8051/trunk/rtl/verilog/oc8051_tc.v
116	change sfr's interface.	simont	7733d 08h	/8051/trunk/rtl/verilog/oc8051_tc.v
112	change timers to meet timing specifications (add divider with 12)	simont	7736d 12h	/8051/trunk/rtl/verilog/oc8051_tc.v
82	replace some modules	simont	7817d 08h	/8051/trunk/rtl/verilog/oc8051_tc.v
46	prepared header	simont	7922d 05h	/8051/trunk/rtl/verilog/oc8051_tc.v
17	fix some bugs	simont	7966d 09h	/8051/trunk/rtl/verilog/oc8051_tc.v
4	Code repaired to satisfy the linter; testbech fails	markom	7969d 11h	/8051/trunk/rtl/verilog/oc8051_tc.v
2	Initial CVS import	simont	7985d 09h	/8051/trunk/rtl/verilog/oc8051_tc.v