OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Rev 82

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
82 replace some modules simont 7817d 12h /8051/trunk/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7886d 09h /8051/trunk/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7894d 11h /8051/trunk/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7899d 09h /8051/trunk/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7905d 07h /8051/trunk/rtl/verilog/oc8051_top.v
46 prepared header simont 7922d 08h /8051/trunk/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 7949d 11h /8051/trunk/rtl/verilog/oc8051_top.v
28 remove syn signal simont 7960d 15h /8051/trunk/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7960d 17h /8051/trunk/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 7963d 07h /8051/trunk/rtl/verilog/oc8051_top.v
17 fix some bugs simont 7966d 12h /8051/trunk/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 7967d 10h /8051/trunk/rtl/verilog/oc8051_top.v
9 removed unused compare states markom 7969d 09h /8051/trunk/rtl/verilog/oc8051_top.v
8 some IDS optimizations markom 7969d 10h /8051/trunk/rtl/verilog/oc8051_top.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 7969d 11h /8051/trunk/rtl/verilog/oc8051_top.v
5 more linter corrections; 2 tests still fail markom 7969d 13h /8051/trunk/rtl/verilog/oc8051_top.v
4 Code repaired to satisfy the linter; testbech fails markom 7969d 15h /8051/trunk/rtl/verilog/oc8051_top.v
2 Initial CVS import simont 7985d 12h /8051/trunk/rtl/verilog/oc8051_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.