URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Rev 119

Rev	Log message	Author	Age	Path
119	remove signal sbuf_txd [12:11]	simont	7731d 02h	/8051/trunk/rtl/verilog/oc8051_uart.v
116	change sfr's interface.	simont	7733d 20h	/8051/trunk/rtl/verilog/oc8051_uart.v
115	change uart to meet timing.	simont	7733d 22h	/8051/trunk/rtl/verilog/oc8051_uart.v
82	replace some modules	simont	7817d 21h	/8051/trunk/rtl/verilog/oc8051_uart.v
46	prepared header	simont	7922d 18h	/8051/trunk/rtl/verilog/oc8051_uart.v
36	fix bugs in mode 0	simont	7949d 20h	/8051/trunk/rtl/verilog/oc8051_uart.v
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7960d 23h	/8051/trunk/rtl/verilog/oc8051_uart.v
17	fix some bugs	simont	7966d 21h	/8051/trunk/rtl/verilog/oc8051_uart.v
10	% replaced with ^ in uart; some minor improvements	markom	7968d 02h	/8051/trunk/rtl/verilog/oc8051_uart.v
8	some IDS optimizations	markom	7969d 19h	/8051/trunk/rtl/verilog/oc8051_uart.v
5	more linter corrections; 2 tests still fail	markom	7969d 22h	/8051/trunk/rtl/verilog/oc8051_uart.v
4	Code repaired to satisfy the linter; testbech fails	markom	7970d 00h	/8051/trunk/rtl/verilog/oc8051_uart.v
2	Initial CVS import	simont	7985d 22h	/8051/trunk/rtl/verilog/oc8051_uart.v