URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5512d 21h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
185		root	5568d 22h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
138	Change buffering to save one clock per instruction.	simont	7704d 20h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
136	registering outputs.	simont	7705d 01h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
127	fix bug (cyc_o and stb_o)	simont	7724d 02h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
110	change adr_i and adr_o length.	simont	7736d 17h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
82	replace some modules	simont	7816d 22h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v
73	initial import	simont	7893d 19h	/8051/trunk/rtl/verilog/oc8051_wb_iinterface.v