OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_dwbif.v] - Rev 203

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
203 optimised exception signals. sybreon 5432d 20h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
202 added basic exception signals. sybreon 5432d 20h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
191 New directory structure. root 5562d 23h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
147 Disconnect from pipeline. sybreon 5879d 01h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
134 Minor performance improvements. sybreon 5880d 00h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5880d 16h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
127 Fixed pipelined latching of data bug. sybreon 5883d 03h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
125 Passes arithmetic tests with single thread. sybreon 5885d 05h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
120 Basic version with some features left out. sybreon 5886d 01h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v
118 Initial import. sybreon 5888d 17h /aemb/trunk/rtl/verilog/aeMB2_dwbif.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.