URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [sim] - Rev 11

Rev	Log message	Author	Age	Path
11	Corrected a small problem with the KAT testbench.	motilito	4053d 23h	/aes_highthroughput_lowarea/trunk/verilog/sim
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4454d 22h	/aes_highthroughput_lowarea/trunk/verilog/sim
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	4909d 21h	/aes_highthroughput_lowarea/trunk/verilog/sim
5	Updating sub-directory structure	motilito	4910d 01h	/aes_highthroughput_lowarea/trunk/verilog/sim
3	Building new directory structure.	motilito	4910d 11h	/aes_highthroughput_lowarea/trunk/verilog/sim