URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [axi4-stream-bfm-master.vhdl] - Rev 14

Rev	Log message	Author	Age	Path
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	3900d 10h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	3900d 15h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
11	Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match.	daniel.kho	3911d 14h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
9	Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages.	daniel.kho	3918d 10h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl