URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] [virtual_jtag_adda_trig.v] - Rev 9

Rev	Log message	Author	Age	Path
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4449d 21h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_adda_trig.v
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4454d 21h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_adda_trig.v
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4457d 21h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_adda_trig.v
2	Checked in working code base.	ash_riple	4461d 20h	/bustap-jtag/trunk/rtl/altera/virtual_jtag_adda_trig.v