URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] [csa/] [trunk/] [sw_sim/] [misc.h] - Rev 52

Rev	Log message	Author	Age	Path
52	add the macro DEBUG_OUTPUT for the general debug information output	simon111	5165d 19h	/csa/trunk/sw_sim/misc.h
40	add timescale.v file and fix a bug in key_schedule module	simon111	5532d 09h	/csa/trunk/sw_sim/misc.h
34	add binary test date (only sw_sim now )	simon111	5533d 20h	/csa/trunk/sw_sim/misc.h
24	New directory structure.	root	5572d 01h	/csa/trunk/sw_sim/misc.h
22	decrypt module testbench update	simon111	5695d 08h	/csa/trunk/sw_sim/misc.h
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5709d 07h	/csa/trunk/sw_sim/misc.h
17	finish block_decypher module	simon111	5770d 15h	/csa/trunk/sw_sim/misc.h