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[/] [dblclockfft/] [trunk/] [bench/] [cpp/] [mpy_tb.cpp] - Rev 30

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30 Minor documentation edits. dgisselq 3106d 22h /dblclockfft/trunk/bench/cpp/mpy_tb.cpp
29 Checking in a lot of changes here. These changes were focused on two
things primarily: 1st the ability to match, in bench testing, the bench
test to the configuration of the generated FFT. For this purpose, the
fftgen program now creates fftsize.h and ifftsize.h header files. These
header files contain the parameters that were used in the creation of the
various verilog files, and therefore the C++ test benches may now be compiled
to match the test files. The 2nd change is the multiply. Based upon a
set of slides from Xilinx, I rebuilt my shiftaddmpy into a longbimpy.
(Think if 'bimpy' as a 'bi', or two-bit, 'mpy', or multiply.) Longbimpy
depends upon bimpy, an optimized 2xN bit multiply--optimized for 6-bit
LUTs with carry chains. Longbimpy simply expands that capability to a
NxN bit multiply. Sadly, the longbimpy approach increased my area on the
chip when it was supposed to be a cheaper multiply, so I may well take it
back out in the future.		 dgisselq 3263d 07h /dblclockfft/trunk/bench/cpp/mpy_tb.cpp
6 Lots of work accomplished today. Test benches now exist and work for the:
butterfly, multiply, bitreversal, pairwise FFT stage (dblstage), and the
four-wise FFT stage (qtrstage). Work continues on the single (generic)
FFT stage, and (of course) the FFT isn't ready yet. A second commit will
follow this one shortly with the new files added (oops!--I should've added
them this time--my bad.)		 dgisselq 3389d 19h /dblclockfft/trunk/bench/cpp/mpy_tb.cpp
4 Bench tests updated, they now state SUCCESS upon successful completion,
return a 0 on success, and all bench tests test all function outputs
(now).		 dgisselq 3390d 07h /dblclockfft/trunk/bench/cpp/mpy_tb.cpp
3 The first upload of the s/w didn't take. Had it taken, the comment would've
been: This is the first upload of the double clocked FFT software. While it
should (roughly) be complete, a lot of work remains to be done--primarily
in building test benches, modifying the interface of fftgen to make it
more friendly, etc. In fact, the c++ code not only compiles, but the
Verilog code it produces actually builds as well!

Now, however, I have several test benches written, and have verified the
unit functionality of the multiply, bit reversal stage, the dblstage (FFT
len 2), and the qtrstage (FFT len 4). I then took a closer look at the
multiply, discovered it failed at signed integers and rebuilt it. The
new test bench tests the full 16-bit signed integer support properly. This
leaves butterflies and generic FFT stages that still need test benches, as
does the main (I)FFT program.		 dgisselq 3390d 08h /dblclockfft/trunk/bench/cpp/mpy_tb.cpp

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