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[/] [ha1588/] [trunk/] [sim/] [rtc/] [rtc_timer_tb.v] - Rev 58

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58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4420d 07h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
47 Added test case of -16 negative period_adj value, to show the effect trying to set time backwards. Thanks to Frank Yang's question. edn_walter 4428d 13h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
42 Updated RTC testbench. Shrunk 1s to 1us to simulate more cycles during a short time. edn_walter 4433d 03h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4433d 04h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4434d 05h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4434d 09h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
34 Added LGPL file header to all copyrighted files. edn_walter 4436d 06h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4446d 03h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4452d 23h /ha1588/trunk/sim/rtc/rtc_timer_tb.v
3 Added function block RTC and its unit test. ash_riple 4470d 22h /ha1588/trunk/sim/rtc/rtc_timer_tb.v

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