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[/] [ima_adpcm_enc_dec/] [trunk/] [verilog/] [rtl/] [ima_adpcm_enc.v] - Rev 3

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3 Added Altera FPGA synthesis results to the specifications document.
Changed an assignment statement in the encoder module to clear a synthesis warning.
motilito 4636d 14h /ima_adpcm_enc_dec/trunk/verilog/rtl/ima_adpcm_enc.v
2 Initial core version motilito 4641d 16h /ima_adpcm_enc_dec/trunk/verilog/rtl/ima_adpcm_enc.v

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