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[/] [ion/] [trunk/] [vhdl/] [tb/] [mips_tb_pkg.vhdl] - Rev 251

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Rev Log message Author Age Path
251 Extracted COP0 logic to separate module within CPU.
Preliminary step for COP0 refactor.
No change in functionality.		 ja_rd 3799d 08h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
226 Updated demo and test bench to use new SoC entity. ja_rd 4372d 20h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
206 Fixed SygnalSpy function calls for compatibility with older versions of Modelsim ja_rd 4662d 15h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.		 ja_rd 4699d 05h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
157 Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated		 ja_rd 4752d 07h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4752d 16h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
112 Updated simulation package for compatibility to new cache ja_rd 4815d 19h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
96 CPU rd and wr data address buses unified ja_rd 4848d 19h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4859d 16h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 4870d 06h /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl

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